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一种快速有限域乘法器结构及其VLSI实现 被引量:4

A Fast Finite Field Multiplier Architecture and Its VLSI Implementation
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摘要 提出了一种快速有限域乘法器结构。将多项式被乘数与乘数各自平分成两个子多项式,并使用数字乘法结构计算这些子多项式的乘积。通过改变数字乘法结构的数字大小D,来均衡乘法器性能和实现复杂度。为了简化模不可约多项式f(x)运算,采用特殊多项式AOP(allonepolynomials)和三项式,产生有限域GF(2m)。这种乘法器与LSD乘法器相比,在数字大小D相同时,可将运算速度提高1倍。这种乘法器结构适合高安全度密码算法的VLSI设计。 A fast finite field multiplier is proposed in this paper. The architecture equally divides the multiplicator and multiplicand of field multiplication into two sub-polynomials, respectively, whose products are calculated by the digit multiplier. To simplify reduction modulo, special polynomials are used to generate finite field GF(2m), such as AOP (all one polynomials) and trinomials. Compared to the traditional LSD multiplier, the proposed multiplier is two times faster. In addition, this multiplier structure is suitable for VLSI design of high-security cryptographic algorithms.
出处 《微电子学》 CAS CSCD 北大核心 2005年第3期314-317,共4页 Microelectronics
基金 国家高技术研究发展(863)计划资助项目--高性能加密芯片设计项目(2003AA141040)
关键词 VLSI 有限域 乘法器 椭圆曲线密码 VLSI Finite field Multiplier Elliptic curve cryptosystems(ECC)
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参考文献9

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同被引文献36

  • 1袁丹寿,戎蒙恬,陈波.一种并行的有限域乘法器结构[J].上海交通大学学报,2005,39(4):636-639. 被引量:3
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