一种用于LVDS驱动器的PLL时钟倍频器的设计

Design of a PLL Clock Frequency Multiplier for LVDS Driver

设计了一个结构新颖的3.5倍频锁相环(PLL)倍频器,该电路应用自适应电荷泵和压控振荡器工作频率范围复用技术,调整环路带宽,减小压控振荡器的工作范围。采用1stSilicon0.25μmCMOS混合信号工艺仿真。结果表明,PLL倍频器具有较低的噪声和较高的捕获速度。

A 3.5 times PLL clock frequency multiplier for LVDS driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth, and a VCO is designed with frequency range reuse technology. The circuit is implemented using 1 st Silicon 0.25 μm mixed-signal CMOS process. Simulation results show the PLL clock frequency multiplier has lower phase noise and shorter capture time.