基于CPLD的简易逻辑分析仪设计

Design of logic analyzer based on oscilloscope displaying

以CPLD可编程逻辑器件为控制核心,以VHDL语言为设计工具,利用CPLD逻辑性强的优势,综合CPLD、常规数字和模拟电路技术完成简易逻辑分析仪设计。采用两块D/A芯片作为系统输出,同时提供示波器X、Y轴信号,在模拟示波器上实现同时显示8路信号的功能。该逻辑分析仪可以实现始端触发和终端触发,可根据触发方式分别显示触发前、后所保存的逻辑状态,并显示触发点位置和时间标志线移位。

In this system the CPLD is used as the control core and the VHDL language is used as the design tool. This system accomplishes the functions of the logic analyzer, taking the advantage of the great logicality and synthesizing the technology of CPLD, digital and analogy electronics. The system uses two pieces of D/A to output X and Y axes signals simultaneously, and realizes the function of displaying signals above 8 channels on the oscilloscope at the same time. This logic analyzer can realize the triggering at the beginning or the end, and according the trigger mode it also can display the saved logic states before or after the triggering and triggered position, time line mark.