高速ECL数字电路中的端接技术

Termination Technique of High Speed ECL Digital Circuits

高速数字电路中,各级电路在端接很容易出现信号完整性问题.串行端接是一种在源端进行阻抗匹配的端接技术,使得接收器可以收到完整的信号电压.戴维南并行端接可以有效地抑制过冲和欠冲,使得信号的摆幅缩小,增强了系统的噪声容限.采用上述的端接技术可在高速数字电路中实现信号的完整性传输.

There are problems with signal integrity in high speed digital circuits. Series termination is an impedance matching technology in the source end which allows the receiver to receive integral signal. The parallel termination can effectively suppress overshoot and undershoot that makes the signal swing less and the system noise tolerance larger. With the above technology we obtain signal integrity in the transmission of high speed digital circuits.