基于LPC总线的FPGA高速初始化配置系统设计

Design of FPGA Initialization Configure System at High Speed with LPC Bus

介绍了一种FPGA初始化配置的方法。根据FPGA配置的基本原理,基于LPC总线协议,采用CPLD+Super-Flash模式。以高速Flash芯片49LF008A作为配置数据的存储器件,对CPLD器件XC95144编程产生实现初始化配置的时序逻辑,并实现LPC总线接口控制功能。设计出的基于LPC总线的配置电路,由于采用从并模式和存储芯片的高速读取,使得FPGA初始化配置速度得到极大提高,配置电路得到简化,同时实现配置系统成本降低的外在需求。

A method of FPGA initialization configure is introduced. The function is carried out in the mode of CPLD + Super-Flash and with LPC bus, which is according to the essential initialization configure principle. The 49LF008A chip, a kind of high-speed flash memory, acts as memory for initialization configure data, and the initialization configure timing-logic and the function of LPC bus interface are gained via programming on the CPLD device XC95144. The speed of FPGA initialization configure becomes high a lot for reading data from memory at high speed and the system working in slave -parallel mode, at the same time, the need of lowing cost is met when the circuit becomes simple.