TFT阵列栅延迟特性研究

Study on TFT Array Gate Delay Characteristics

对 TFT 栅延迟进行了研究。为使栅延迟最小,对栅总线结构进行了优化,并用分布参数理论与正弦稳态法分析了该结构。最后在一定近似条件下,得到优化结构尺寸的原理性结果。

The theory study on TFT array gate delay is introduced.The structure of the gate bus was optimized to limit gate delay,and the distributed RC system and sinusoid stationary analysis were employed.A optimized structure was obtained under some condi- tions.