摘要
本文基于数据驱动原理提出并用FPGA实现了MPEG-2MP@HL的视频解码器。该解码器中的各个模块具有高内聚,低耦合的特点。只要各个模块符合数据驱动的工作方式,模块就能自我正常工作。由于视频数据和控制数据分开,能够节省各个模块占用的存储器资源。另外,对SDRAM读写上作了一定的优化。
A compact and high efficiency MPEG-2 MP@HL video decoder is presented based on data driven. The modules of decoder are of high cohesion and low coupling. If the state of module accords to the working modes of data driven, the module will work spontaneously. Because of depart of video data and control data,the decoder can reduce storage of all modules and hardware spending. In addition the decoder has a certain extent optimize of SDRAM.
出处
《微计算机信息》
北大核心
2005年第06X期51-52,116,共3页
Control & Automation
