PCI总线多用户数据缓冲区管理器的实现

Implementation of PCI Bus Multi-user Data Buffer Manager

分析了一种PCI总线上支持多个用户的数据缓冲区管理器电路所采用的电路结构,给出了关键点的仿真波形。从理论上分析了用户的缓冲区分配原则、端口总线带宽、用户最大服务等待时间和最小缓冲区数量等工作参数。给出了多用户缓冲区管理器中所需要最小存储区的计算方法。以分析为基础,采用XILINX的XCV600EPQ240实现了128用户缓冲区管理器电路,并在实际系统中进行了测试和验证。

The circuit structure of a kind of PCI bus multi-user data Buffer Manager (BM) is analyzed in this paper, and typical simulating waveform is presented. The method to allocate the data buffers, port bandwidth, maximum user waiting time and minimum user buffer requirements are analyzed theoretically. The expression to calculate the minimum memory needed in the BM is given. Based on the analysis, a 128-user buffer manager is realized with XILINX XCV600EPQ240 and verified in application systems.