数据传输系统中的定时抖动

Timing Jitter in Data Transmission system

本文介绍了通过数字锁相环（ＤＰＬＬ）减弱定时抖动的分析计算方法。导出了不经过积累，经过不同方法积累进行相位调整时的抖动改善量计算公式，并给出抖动改善量与有关参数的关系曲线，可作为数据传输系统设计定时环路的参考。

This paper describes an algorithm using digital phase locked loop(DPLL)to reduce timing jitter.The author derived calculating expressions for the improved rate of jitter,using different ways to adjust thephase. The charactic graphers between the improved rate of jitter and parameters relating to jitter were givenin this paper.This method can be used for desgning timing loop in data transmission system.