摘要
介绍一种以ASIC(专用集成电路)实现为目的的数字循环相关器结构。基本思想是将快速算法与并行处理技术结合起来,以达到较高的工作速度而硬件开销又不致太大这个目标。讨论了累接算法及其运算量,然后根据累接算法给出了循环相关器的流水线结构,并分析这种结构的硬件开销及延迟级数。分析表明累接算法与流水线技术的结合是一种提高数字循环相关器综合指标的有效方法,并且所得的结构具有较好的规律性和简洁性,便于硬件实现。
This paper presents a kind of digital cyclic correlator structure for realization in applicationspecific integrated circuit(ASIC).The idea is to combine the techniques of fast algorithm and parallelprocessing in order that the working speed is much higher but the scale of hardware is not too large.Afterinterated algorthms and their computation complexity are studied,a pipeline structure of cyclic correlator isgiven based on the interated algorithm,the hardware scale and the delay of this structure are aiso analysed.It is concluded that the combination of interated algorithms and pipeline techniques is effective to increasecomprehensive quality index,and the obtained structure good in regularity and simplicity,which is helpfulto hardware realization.
出处
《电子科技大学学报》
EI
CAS
CSCD
北大核心
1995年第2期126-130,共5页
Journal of University of Electronic Science and Technology of China
基金
国防科工委预研基金
关键词
循环相关
累接算法
并行处理
专用集成电路
cyclic correlation
interated algorithm
parallel processing
pipeline