HCE：一个层次化VLSI版图的电路提取系统

HCE:A Hierarchical Circuit Extractor For VLSI

本文采用基于边的线扫描算法的图形逻辑操作，并以此为基础设计了一个层次化的电路提取器（ＨＣＥ），单元重复利用率越高，层次化的电路提取器ＨＣＥ比平面化的电路提取器的速度越快，并且，本提取器ＨＣＥ能够处理非曼哈顿图形，提取器ＨＣＥ系统是在ＨＰ９０００／８３４图形工作站上开发完成的，该系统采用了已成为工业标准的软件开发环境，即ＵＮＩＸ操作系统，Ｘ窗口，Ｃ语言和ＥｔｈｅｒＮｅｔ网络，便于系统移植、维护和再开发。

The hierarchical circuit extractor(HCE) is developed on the basis of edge-based scanline algorithm.The HCE is much faster(for actual designs) than the methods that ignore hierarchy.And the HCE can process non-manhaton pattern.The system is implemented on HP9000/834 graphic workstation under the industrial standard software development environment such as UNIX operation system,X windows.C language and Ethernet network for the system portability,maintenance and redevelopment.