边界扫描可测性设计及其VHDL描述

Boundary Scan Design for Testability and Its Description Language VHDL

用传统方法测试高密集度ＳＭＴ板是难以想象的，边界扫描可以解决这一问题。在这基础上讨论了边界扫描可测性设计技术及其硬件描述语言ＶＨＤＬ．

Testing high density SMT boards with traditional methods can be a nightmare,but boundary scan can relieve this problem. This Paper discusses the design for testability with boundary scan and its hardware description language VHDL.