单输出组合网络的TLU　FPGA的逻辑映射

TLU-BASED FPGA LOGIC MAPPING FOR SINGLE-OUTPUT COMBINATIONAL NETWORK

基于真值表结构的ＦＰＧＡ，即ＴＬＵ（ＴａｂｌｅｏｆＬｏｏｋ－Ｕｐ）ＦＰＧＡ是一种颇具代表性的ＦＰＧＡ结构。在本文中作者针对单输出组合网络，提出并实现了对面积和延迟进行折衷考虑的ＴＬＵＦＰＧＡ的逻辑映射算法，它综合了面积驱动的Ｃｈｏｒｔｌｅ－ｃｒｆ及延迟驱动的Ｃｈｏｒｔｌｅ－ｄ的优点。这为进一步将该算法拓展至实际的多输出组合网络乃至同步时序网络打下了基础。

TLU-Based FPGA is a very popular FPGA architecture. In this paper, we present an improved algorithm for single-output combinational network, which integrates the advantages of the area-driver Chortle-crf and the delay-driver Chortle-d.This makes it possible for the extension of our algorithm to multiple-output combinational network and even sequential network.