CMOS ASIC设计中减小时延的途径

Approaches to Reducing Time Delay in CMOS ASIC Design

工作主频是ＡＳＩＣ最重要的设计指标之一，而减小延迟是提高主频的基本途径。本文人逻辑和工程设计的角度介绍减小路径延迟的主要方法。

Main frequency is one of the most important targets of ASIC designand the reduction of time delay is the basic method of increasing main frequncy.This pa-per describes commonly used ways to reduce path delay.