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JTAG边界扫描单元的改进方案 被引量：1

An improved scheme of JTAG boundary-scan cell
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摘要 首先分析了边界扫描系列协议的现状,指出近期的工业标准仍将只有IEEEstd1149.1.为了能够检测电容耦合故障,对JTAG规定的边界扫描单元进行了简单的修改.修改之后的扫描单元在不影响JTAG定义功能的同时,增加了对耦合电容的故障检测能力. The current situation of the boundary scan protocol family was analyzed firstly. It was pointed out that IEEE Std 1149. l would still be the only standard of industry. But in reality,capacitance coupling is very popular for conjunction between devices. In order to locate the fault of this kind, modification is be made for the original structure of boundary scan cell. The modified cell has the function to diagnose the capacitance fault in addition to the original function.
作者 陈新武 李建国
机构地区 信阳师范学院物理电子工程学院 华中科技大学图象识别与人工智能研究所IC设计中心 郑州师专物理系
出处 《信阳师范学院学报（自然科学版）》 CAS 北大核心 2005年第3期329-332,共4页 Journal of Xinyang Normal University(Natural Science Edition)
基金 国家自然科学基金资助项目(90207020)
关键词 JTAG 边界扫描单元 电容耦合 JTAG bundary-scan cell capacitor-coupling
分类号 TP216 [自动化与计算机技术—检测技术与自动化装置]
  • 相关文献

参考文献9

  • 1DELLECKER R.Boundary-scan bursts into the modem production facility[J].IEEE Aerospace and Electronics Systems Magazine,2001,16(6):21-24.
  • 2Supplement to IEE std 1149.1-1990.IEEE standard test access port and boundary-scan architecture[S].
  • 3IEEE Std 1149.5-1995.IEEE Standard for Module Test and Maintenance Bus (MTM-Bus)Protocol[S].
  • 4IEEE Std 1149.4-1999.IEEE Standard for a Mixed Signal Test Bus[S].
  • 5IEEE Std 1149.1-2001.IEEE Standard Test Access Port and Boundary-Scan Architecture[S].
  • 6IEEE Std 1149.6-2003.IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks[S].
  • 7PARKER K P.Boundary-Scan testing of AC coupled nets[A].Proc on Int'l Test Conf[C].Baltimore,USA:IEEE Press,2001.1188.
  • 8CHUNG S,BAEG S.AC-JTAG:Empowering JTAG beyond testing DC nets[A].Proc on Int'l Test Conf[C].Baltimore USA:IEEE Press,2001.30-37.
  • 9KAC U;NOVAK F;AZAIS F,et al.Extending IEEE Std.1149.4 analog boundary modules to enhance mixed-signal test[J].Design & Test of Computers,2003,20(2):32-39.

同被引文献5

  • 1陈新武,陈朝阳.SOC的低功耗快速测试[J].半导体技术,2004,29(11):1-4. 被引量：1
  • 2Girard P. Survey of Low-Power Testing of VLSI Circuits[J]. IEEE Design and Test of Computers (S0740-7475), 2002, 19(3) :82-92.
  • 3Chou R, Saluja K, Agrawal V. Scheduling Tests for VLS1 Systems Under Power Constraints[J]. IEEE Trans Very Large Scale Integration (VLS1) Systems (S1063-8210), 1997, 5 (2):175-185.
  • 4Nourani M, Chin J. Test Scheduling with Power-Time Tradeoff and Hot-Spot Avoidance Using MILP [ J ]. Computers and Digital Techniques (S1350-2387), 2004 (9): 341 -355.
  • 5Zhao D, Upadhyaya S J. A Generic Resource Distribution and Test Scheduling Scheme for Embedded Core-Based SoCs[J]. IEEE Transactions on Instrument and Measurement (S0018-9456), 2004,53 (2) :318 -329.

引证文献1

信阳师范学院学报（自然科学版）
2005年 第3期

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