Patterned Dual pn Junctions Restraining Substrate Loss of an On-Chip Inductor

放射状双pn结抑制片上电感衬底损耗(英文)

Dual pn junctions in lateral and vertical directions are formed by diffusing the p^＋ on the patterned n-well in standard CMOS technology, which are inserted under the inductor in order to reduce the currents in the substrate induced by the electromagnetic field from the inductor. The thickness of high resistance is not equivalent to the width of the depletion region of the vertical pn junctions,but the depth of the bottom pn junction in the substrate are both proposed and validated. For the first time, through the grounded p^＋-diffusion layer shielding the suhstrate from the electric field of the inductor, the width of the depletion regions of the lateral and vertical pn junctions are changed by increasing the voltage applied to the n wells. The quality factor is improved or reduced with the thickness of high resistance by 19%. This phenomenon validates the theory that the pn junction substrate isolation can reduce the loss caused by the currents in the substrate induced by the electromagnetic field from the inductor.

使用标准CMOS工艺,在放射状的n阱上面扩散p+,使垂直和水平方向形成双pn结,将此结放在电感的底部用来抑制衬底损耗.提出并实验证明了该结构形成的高阻区厚度不是垂直pn结耗尽层的厚度,而是最低层的pn结的深度.首次通过接地的p+扩散层屏蔽电感到衬底电场,水平和垂直pn结耗尽层厚度随着pn结反向偏压升高改变衬底有效的高阻区厚度,电感品质因数跟随高阻区厚度升降,有效地证明了pn结衬底隔离可以降低电感的衬底电流造成的损耗.