超深亚微米LDD nMOSFET中的非幸运电子模型效应

Nonlucky Electron Model Effect in Ultra-Deep Submicro LDD nMOSFETs

通过对采用0.18μmCMOS工艺制造的两组不同沟道长度和栅氧厚度的LDD器件电应力退化实验发现,短沟薄栅氧LDDnMOSFET(Lg=0.18μm,Tox=3.2nm)在沟道热载流子(CHC)应力下的器件寿命比在漏雪崩热载流子(DAHC)应力下的器件寿命要短,这与通常认为的DAHC应力(最大衬底电流应力)下器件退化最严重的理论不一致.因此,这种热载流子应力导致的器件退化机理不能用幸运电子模型(LEM)的框架理论来解释.认为这种“非幸运电子模型效应”是由于最大碰撞电离区附近具有高能量的沟道热电子,在Si SiO2界面产生界面陷阱(界面态)的区域,由Si SiO2界面的栅和漏的重叠区移至沟道与LDD区的交界处以及更趋于沟道界面的运动引起的.

This paper presents the degradation characteristics of two groups of LDD nMOSFETs with different channel length and gate oxide thickness that are fabricated on 0.18μm CMOS technology. It is found that in 0. 18μm nMOSFETs the device lifetime under channel hot-carrier （CHC） stress is lower than that under drain avalanche hot-carrier （DAHC） stress,contrary to the usual thinking that the worst case stress condition depends on the gate voltage with the maximum substrate current. Therefore, the hot-carrier stress-induced device degradation in 0. 18μm nMOSFETs cannot be explained in the framework of the lucky electron model（LEM）. Our investigation suggests that such a “non-LEM effect” may be due to the fact that the increased inter-face trap （interface state） generation region at the Si-SiO2 interface by the channel hot electrons with high energy near the maximum impact ionization site moves from the lightly doped drain （LDD） diffusion region to the boundary of the bulk and LDD region beneath the gate oxide. The current path is located closer to the Si-SiO2 interface.