基于DBL结构的嵌入式64kb SRAM的低功耗设计

Low power design of the embedded 64kb SRAM based on the DBL approach

针对嵌入式系统的低功耗要求,采用位线分割结构和存储阵列分块译码结构,完成了64kb低功耗SRAM模块的设计.与一般布局的存储器相比,采用这两种技术使存储器的功耗降低了43%,而面积仅增加了18%.

To meet the low power requirement of the embedded system, a 64 kb-embedded SRAM module is designed by adopting the DBL approach and the proposed memory array Divided Block Decoding approach.Compared with the common memory structure, the power decreases by 43%, while the area increases only by 18%.