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多通道LVDS的实现及传输错误处理 被引量:6

Multi-Channel LVDS and Transmission Error Handling
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摘要 低电压差分信号LVDS是下一代通讯协议采用的数据传输形式.结合并行RapidIO协议的实现给出了用CPLD器件及VHDL语言实现多通道LVDS的方法;详细讨论了多数据通道高速数据传输时由于时钟-数据错位和数据线间延迟差异引起的传输错误;对这种传输错误处理有几种解决方案,论文采用4位通道对齐器消除4位以内的传输错误,给出了通道对齐器的实现方法及仿真波形;在RapidIO协议验证板上验证了多通道LVDS数据传输的实现方法,并通过实验测得8位并行LVDS的数据传输率可达300MB/秒,实验表明多通道LVDS实现简单,抗干扰能力强. ow voltage differential signal, or LVDS, is adopted by the next-generation communication protocol, such as RapidlO interconnect. In this paper, the method to implement the multi-channel LVDS using CPLD device and VHDL language is presented first. All sorts of transmission error, which are generated during the process of high-speed data transportation due to clock-data skew and difference between transmission lines, are also discussed in detail. A logical component, 4-bit-channel aligner is devised and simulated to solve this sort of transmission error. Finally an evaluation board of RapidIO are devised, on which multi-channel LVDS is implemented. The transmission ratio of 8-bit parallel LVDS on this hoard is up to 300MBps.Many experiments demonstrate that multi-channel LVDS has perfect character of high transportation ratio, easy implementation, and high EMIF.
作者 李向阳
出处 《小型微型计算机系统》 CSCD 北大核心 2005年第8期1436-1440,共5页 Journal of Chinese Computer Systems
基金 国家重点基础研究发展规划项目(G1999032906)资助.
关键词 低电压差分信号 RAPIDIO 时钟-数据错位 通道对齐器. LVDS rapidIO clock-data skew channel aligner
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参考文献14

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同被引文献23

  • 1布明恩,杨文荣,张启平.8位LVDS串行器的设计研究[J].微计算机信息,2005,21(1):103-104. 被引量:4
  • 2Kannan Srinivasagam ,David Mahashin.针对高速接口的源同步时钟实现方案的研究[J].电子设计应用,2005(4):93-94. 被引量:4
  • 3毛继志,李建周,许家栋.基于FPGA的高速数传系统研究[J].微电子学与计算机,2005,22(11):104-107. 被引量:7
  • 4苗澎,王志功,李彧.万兆以太网物理层技术[J].电路与系统学报,2006,11(2):69-73. 被引量:5
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  • 9夏宇闻,Verilog数字系统设计教程[M],北京航天航空大学出版社,2007年1月.
  • 10Michael D.Ciletti著张雅绮李锵等译,Verilog HDL高级数字设计[M],电子工业出版社,2007年1月.

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