摘要
系统阐述了USB1.1OHCI主机控制器IP的功能、结构、各功能模块的电路设计和实现方法,介绍了主机串行接口引擎模块及其时钟和数据恢复电路以及并行CRC算法的设计。为了验证OHCI主机控制器功能正确性,在中科SoC虚拟验证平台上对该主机控制器做了系统级模拟验证,验证结果证明了设计的正确性。
This paper presents the function, architecture, the sub-module circuit design and implementation of USB 1.1OHCI host controller IP. It addresses the host controller serial engine and its clock and data recovery circuit and parallel cyclic redundancy check (CRC) arithmetic. To verify the OHCI host controller's function, the system level verification is done on the ZhongKe-SoC virtual verification platform, and the results demonstrate the correctness of the design.
出处
《计算机工程》
EI
CAS
CSCD
北大核心
2005年第15期37-38,67,共3页
Computer Engineering
基金
国家"863"计划基金资助项目"高速32位嵌入式CPU开发"(2002AA1Z1040)
关键词
USB主机控制器
开放主机总线接口
数字锁相环
CRC
USB host controller
Open host controller interlace (OHCI)
Digital phase lock loop (DPLL)
CRC