JPEG2000分数位平面编码器的FPGA电路实现

FPGA Implementation of JPEG2000 Fractional Bit-plane Encoder

分数位平面编码是JPEG2000图像压缩国际标准中的核心技术之一,是影响JPEG2000编码速度的最关键部分。基于位平面、过程双重并行(BPDP)的编码方法和局部模块并行结构,利用FPGA电路设计了JPEG2000分数位平面编码器。电路仅需要约5100个逻辑单元,当工作在54MHz时,每秒可以编码30幅尺寸约为1500×1200的图像。

The fractional bit-plane coding is one of the key technologies in JPEG2000, and is the bottleneck for fast JPEG2000 coding. JPEG2000 is the new image compression international standard. The fractional bit-plane encoder is designed based on the bit-plane and pass dual parallel method and the partial-parallel architecture by using FPGA. The design only needs about 5100 logic cells and can encode 30 frames with the size of 1500×1200 pixels per second when it works at 54MHz frequency.