摘要
对高性能乘加单元的设计原理与方法进行了研究,采用改进的Booth算法设计乘法器,提出了一种新的实现这种算法的内部电路逻辑结构。采用这种结构设计MAC单元,大大提高了MAC单元的速度和性能。
Research has been carried on the design theory and method of a design of high performance MAC unit. The modified Booth algorithm is used to design the multiplier and a new booth coding logic circuit is designed. The speed and performance of the MAC is high improved in this configuration designed.
出处
《计算机测量与控制》
CSCD
2005年第7期713-714,736,共3页
Computer Measurement &Control
基金
上海市科委基础研究基金资助项目(02DJ14034)
上海市科委技术攻关基金资助项目(025911323)
