SoC接口综合的层次化通信模型

Hierarchical Communication Model for Interface Synthesis in System-on-Chip Design

以自主研发的软硬件协同设计平台YH-PBDE为基础,提出一个逐层细化的层次化通信模型.该模型遵循计算与通信相分离的设计原则,分为系统、虚部件和实部件三个层次,层与层之间的接口通过映射和细化两种方式实现;同时,基于该模型阐述了一种新颖的虚实部件接口综合算法流程,为不同知识产权核之间的平滑通信提供了实用的解决方案.该模型和方法可以有效地实现不同核之间的自动集成,使复用技术成为可能.

Based on the hardware/software co-design platform environment （YH-PBDE） designed and developed by ourselves, this paper presents a stepwise-refined hierarchical communication model named HCM. This model follows the design tenet that computation and communication should be separated and it consists of three levels： systematic, virtual component and real component. The interface among the three levels is implemented by two methods： mapping and refining. Based on HCM, this paper expatiates on a novel algorithm flow of virtual-real component interface synthesis, providing a useful solution for the smooth communications between various intellectual property （IP） cores. The proposed model and approach can achieve an automatic integration between different IPs effectively, making reuse techniques possible.