一种多倍频选择的高倍频锁相环频率合成器

A PLL Frequency Synthesizer with High Multiple-Frequency

文章描述了一个基准频率为32768Hz的锁相环频率合成器的设计。该频率合成器有1250、1500、2000、2500、3000等5个倍频选择。电路设计基于1stSilicon2.5V0.25μmCMOS工艺。CadenceArtistAnalog仿真显示,该电路可以实现快速锁定,且具有较小的相位抖动。文章研究和总结了频率合成器系统参数的设计理论,对其各个子电路进行了结构优化,并且按MPW流片要求,进行了版图的布局设计。

A phase locked loop （PLL） frequency synthesizer with an input clock of 32 768 Hz is designed, which can generate 5 frequencies with 1 250, 1 500, 2 000, 2 500, and 3 000 as multiplying factors. The design is based on 1st Silicon 2. 5 V 0. 25 μm technology. Simulations using Cadence Artist Analog show that the circuit has a short lockup time with little jitter. Theory on the parameter design of the PLL frequency synthesizer is studied and summarized, and structures of the sub-circuits are optimized. And finally, layout design based on the requirements of MPW is described.