一种4 kb铁电存储器的设计

Design of a 4 k Bit Ferroelectric Memory

以清华大学微电子所的铁电存储器工艺为基础,设计了一个规模为4kb(512×8位)的铁电存储器,包括存储阵列、灵敏放大器、字线位线译码、驱动脉冲产生等模块。设计中,采用新开发的铁电电容模型,文中重点介绍了与传统DRAM、SRAM等存储单元完全不同的铁电存储单元的设计方法。仿真结果表明,铁电存储器在5V工作电压下工作周期为120ns。

A 4 k bit （512×8 bit） FeRAM array is designed with 1μm design rules developed by Institute of Microelectronics of Tsinghua University. The design method for ferroelectric memory, which is quite different from that of conventional memories, such as SRAM and DRAM, is described in particular in the paper. Simulation results show that the device operates at 5 V power supply with a working cycle of 120 ns.