基于乒乓操作的异步FIFO设计及VHDL实现

Design and Implementation of Asynchronous FIFO Based on Ping pong Operation

目前的PLD(可编程逻辑器件)例如FPGA(现场可编程门阵列)凭借其灵活、方便、资源丰富的优势在很多领域得到了广泛应用。随着其片内存储资源的增加,把FIFO(先进先出)器件集成到PLD中是一种方便地代替专用FIFO芯片的实现方法。根据异步FIFO的设计方法,引入乒乓操作的设计技巧,给出了一种用FPGA实现异步FIFO的设计方案。

Programmed Logic Device （PLD） such as FPGA is applied in a wide use because of its flexible, advantageous and wealthy resource. With the increment of the storage in it, it is straightforward to replace dedicated FIFO chip as the FIFO in the PLD. In this article, we introduce the ping-pong operation into the asynchronous FIFO design and provide a FIFO design scheme in FPGA.