摘要
对XT及AT总线的I/OCHRDY信号必须采用集电极开路门(OC门)驱动的说法进行了更正,指出了用三态门(TSL门)代替OC门的充要条件,TSL门代替OC门有助于板级布局布线的简明整洁,提高可靠性,并在FPGA内进行了逻辑实现,逻辑系统运行无误。
The corrections to the concept that I/O CHRDY signal of XT and AT bus must be driven by opencllector （OC） gate are given. The necessary and sufficient condition for substituting OC gate for tristate logic （TSL） gate is described. The substitution method is characterized by higher reliability and better ordered board level routing. The TSL gate integrated in FPGA, as a part of the whole logic system, runs successfully.
出处
《测控技术》
CSCD
2005年第8期72-73,共2页
Measurement & Control Technology
基金
国家自然科学基金资助项目(69774029)
