基于FPGA的高速数字峰值保持器设计

Design of High-Speed Digital Peak Holding Circuit Based on FPGA

分析了模拟峰值保持器的特点,介绍了一种基于现场可编程逻辑器件FPGA与高速A/D转换器的数字式峰值保持电路,并给出了该电路的峰值采集仿真结果。

This paper analyzes the characteristic of the analog peak holding-circuit, introduces a digital peak holding circuit based on FPGA and high-speed A/D converter, and provides its simulation wave in EDA software,