Cache低功耗技术研究

Research of Cache Low Power Technology

现代微处理器中Cache已经成为不可缺少的重要部件,其功耗约占整个芯片功耗的30%￣60%[1,2]。如何减少Cache的功耗,已成为当今Cache设计者关注的焦点。论文提出了一种基于Cache可重组技术以及数据符号压缩技术的低功耗D-Cache设计方法,其技术关键在于动态调整Cache的组织结构,并且改变Cache-Line中数据的存储方式来降低Cache功耗。

Cache is a significant portion in modem microprocessors, Cache accesses consume 30%-60% of total energy dissipation.How to reduce power of Cache has become a focus of many designer of modem Cache,This paper proposes a low-energy D-Cache designing methodology based on resizable Cache,and data sign compression.Its key is to dynamically change the organization of cache and the form of words stored in some cache lines。