摘要
提出了一种分析时序逻辑电路功能的新方法:利用分项满足法和时钟方程来填写状态方程的卡诺图。
The new method was proposed which analyses the function of sequential logical circuit： Karnaugy map of the state equation was filled in by utilizing dividing term - meeting method and clock equation, and the transition map of the state is drawn directly by Karnaugy map.
出处
《通化师范学院学报》
2005年第4期33-36,共4页
Journal of Tonghua Normal University
基金
四川省重点科技项目(02GG006-036)
关键词
时序逻辑电路
卡诺图
状态转换图
时钟方程
sequential logical circuit
Karnaugy map
transition map of the state
clock equation
