使用氩离子击穿PVD阻挡层工艺提高90nm双大马真士革互联的参变量和可靠性(英文)

Improvement in Parametric and Reliability Performance of 90 nm Dual-Damascene Interconnects Using Ar+ PunchthruPVD Barrier Process

随着金属导线线宽的不断缩小,在90nm 技术以下,刻蚀残留物的存在会在应力迁移测试中形成高通孔电阻和空洞成核现象。物理氩离子预清洗是一种去除残留物的有效方法。但在应力迁移测试中发现,底部沟槽铜的二次溅射会导致器件的早期失效。反应性预清洗方法由于含有H +、H 类粒子而在减少C uO x 和清洗Si,N ,F,C ,O ,等蚀刻残留物时表现出其优越性。提出了针对传统PV D 工艺的反应性预清洗及PV D 击穿(沉积,刻蚀,沉积)工艺的解决方案。阻挡层击穿工艺减少了通孔电阻,提高了应力迁移性能,并通过薄钽沉积工序防止了铜的扩散从而保护了双嵌入斜面和错位通孔。此外,使电子阻塞和局部加热效应最小化的U 型界面,提高了电子迁移失效的平均时间,一致的、可重复的覆盖膜特性和良好的电参量测试结果已经证实了这种工艺的生产价值。

As interconnects shrink beyond 90 nm node, the presence of etch residues can create high via resistance and void nucleation during stress migration （SM） testing. Physical Ar＋ preclean is effective in removing residues, but early SM failures have been seen due to Cu resputter from underlying trenches. Reactive preclean methods show promise in reducing CuOx and cleaning Si, N, F, C, O etch residues in presence of H^＋, H^＊ species. In this paper, reactive preclean and PVD PunchThru process （deposit-etch-deposit） is proposed as solution to conventional PVD. The PunchThru process reduces via resistance, improves SM and protects dual-damascene bevel and unlanded vias from Cu diffusion by presence of thin Ta deposition step. In addition, the U-shaped interface, which minimizes electron crowding and localized heating effects, increases the mean time to failure by electromigration. Consistent, repeatable blanket film property and good parametric electrical test results have proven the production worthiness of this process.