CMOS门电路的功率与数据相关性

Correlation between power and data in CMOS gates

为了研究电路实现形式对密码芯片抗“功耗分析攻击”能力的影响,考察了CMOS门电路的交流馈通对电源电流的影响,输入组合对电路充放电网络的影响以及静态电流的数据相关性。对静态逻辑、N/P型动态逻辑和差分Domi-no逻辑的这3种信息泄漏机制进行了具体分析,并对这4种逻辑的2输入与门和或门进行了仿真。静态电路和普通动态电路不同输入变化对应的电流曲线间的最大差值都大于60μA,而差分Domino电路的所有电流曲线之差小于2μA。结果表明:采用N型Domino逻辑,并使数据输入只在时钟为高时有效,相对于其他逻辑功耗信息泄漏要小。

The logic of the VLSI circuit affects the Power Analysis resistance of cryptographic VLSI circuit. This paper analyzes the mechanisms of information leakage in the current of CMOS gates, including the AC coupling, correlations between the charging/ discharging network parameters and the input pattern. The data dependency of the static current is espacially significant. The current traces in static logic, N-type/P-type dynamic logic and differential Domino logic circuits were analyzed and simulated. The maximum differencet between the current plots of the static and the common dynamic gates were larger than 60μA, while the difference for the differential Domino logic circuit was less than 2μA. Therefore, for low information leakage, N-type differential Domino logic circuits should be used with the constraint that data inputs are valid only when the clock signal is high.