VLSI设计仿真系统研究

THE STUDY OF SIMULATION SYSTEM FOR VLSI DESIGN

本文介绍了以国际标准硬件描述语言ＶＨＤＬ作为输入的ＶＬＳＩ设计仿真系统的实现过程，实现了全定制式集成电路的版图设计、模拟验证与分析的全过程；解决了长期以来硬件描述语言不统一的问题；实现了ＶＬＳＩ设计自动化的宿愿；为教学提供了良好的实习环境。

This paper describes the principle and implementation of the VLSI design simulation system,which is based on the international standard language VHDL. It is capable of the full cycle of design, simulating, testing, analysing of the custom made VLSI circuits, It solves the longterm problem concering the un-united of HDL,realizes the desire of VLSI design's automation ,provides a good education enviroment for teaching.