以CPU为核心的数字系统的VHDL建模研究

Modeling Techniques With VHDL in the CPU Based System

本文介绍了ＶＨＤＬ在以ＣＰＵ为核心的数字系统中建模的方法、在算法级上给出ＣＰＵ的功能描述，对ＭＥＮＩＯＲＹ建立简化模型，对接口电路给出信号的定时描述。

This paper discusses modeling techniques withVHDL in the CPU based system. It describes behavioral model of CPU at algorithm level, simpilifiedMEMORY model and presents timing description ofsignals in the interfsce circuits.