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低冗余并行总线容错技术 被引量:1

Fault Tolerance for Low Redundance Parallel Bus
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摘要 本文将从分析Multibus总线功能入手,讨论多种总线容错技术及实时重构总线系统的方法。 The sub system of a distribute computer system communicate via bus so that the fault of bus is fatal. To tolerant the fault of bus is a critical problem. Starting from the analysis of the function of multibus, several techniques of bus fault tolerance and the real time reconfiguration of bus system are discussed in this paper.The effects of these fault tolerant technicals on the reliablity of bus are also discussed in this paper.
出处 《微电子学与计算机》 EI CSCD 北大核心 1995年第6期9-13,共5页 Microelectronics & Computer
关键词 容错技术 并行总线 计算机 Fault tolerance, Rconfiguration,Fault correct, Multibus, Distribute system
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同被引文献6

  • 1Piestrak S J.Design of fast self-testing checkers for a class of Berger codes[J].IEEE Transactions on Computers,1987,36(5):629-634..
  • 2Paschalis A M.Efficient modular design of TSC checkers for m-out-of-n codes[J].IEEE Trans.on Computers,1988,37(3):301-309.
  • 3Anderson D A,Metze G.Design of totally self-checking check circuits for m-out-of-n Codes[J].IEEE Trans.on Computers,1973,22(3):263-269.
  • 4Debaleena Das,Nur A.Touba synthesis of circuits with low-cost concurrent error detection based on bose-lin codes[J].IEEE Trans.on Comput.1996,10:156-161.
  • 5Niraj K.Jha totally self-checking checker designs for bose-lin,Bose,and Blaum Codes[J].IEEE Trans.on Comput,1991,10:137-143.
  • 6张月,李华伟,宫云战,李晓维.考虑串扰影响的时延测试[J].微电子学与计算机,2003,20(11):73-76. 被引量:3

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