新型体系结构概念──虚拟寄存器与并行的指令处理部件

NEW ARCHITECTURE CONCEPTS-VIRTUAL REGISTER AND PARALLEL INSTRUCTION PROCESSING UNIT

随着程序对地址空间的需求日益提高，研究者提出了虚拟存储器概念，使程序访问的地址空间免受物理存储器的限制、随着面向寄存器的ＲＩＳＣ技术发展以及多发射结构中指令调度的日益重要，我们提出了虚拟寄存器的新概念，使寄存器空间不受物理寄存器堆大小的束缚，有利于指令调度和寄存器重新命名技术，提高指令级并行性ＩＬＰ。此外，现代新型ＲＩＳＣ处理机都着重于加强数据处理部件中的执行并行度，忽略了放在存储器中指令的处理。我们提出了与数据处理部件能并行工作的指令处理部件设计；经过预处理的指令流提供给处理数据的多执行部件，从而可以进一步显著提高指令级并行性ＩＬＰ。

Due to the increasing demand to memory space, researchers have proposed theconcept of 'Virtual Memory', which allows the memory addressing space referenced by programs becoming unlimitted. With the rapid development of register-oriented RISC architecture and the increasing importance of exploiting instruction level parallelism, we propose theconcept of 'Vintual Register', which would greatly alleviate the constraints of physical sizeof register file, and offer benefits to instruction scheduling and register renaming technique,therefore greatly increase the instruction level parallelism ILP. Besides, the modern RISCsonly concentrate their emphasis in execution parallelism on data in data - processing unit,usually they have ignored the processing of instructions, which lay in the instruction memorykeeping untouched. In this paper, we propose the concept of instruction processing unit,which operates in parallel with the parallel instruction execution in data -processing unit,After the pre-processing, the instruction stream provided to the multiple execution unitscould have dramatically reduced dependencies, and hence the new architecture proposed inthis paper could significantly increase the ILP and the processor performance.