摘要
应用块浮点算法设计并实现了某雷达接收机数字脉冲压缩系统,着重阐述了块浮点部件的设计原理与实现,并对块浮点、定点算法中截断误差对数字脉冲压缩的影响进行了计算机仿真分析.脉压系统使用FPGA实现,可完成1024点和256点脉压处理,最快时间分别为57.70s和12.65s.
Presents a Digital Pulse Compression （DPC） system which has been used in some Radar receiver. The design and implementation of Block-floating-point components are especially illustrated in detail, Error analysis was given by computer simulation, The compression process can be achieved in 57.70 μs for 1024-point DPC or in 12.65 μs for 256-point DPC.
出处
《河北工业大学学报》
CAS
2005年第4期28-32,共5页
Journal of Hebei University of Technology
关键词
数字脉冲压缩
块浮点
信噪比
截断误差
FPGA
Digital Pulse Compression （DPC）
Block-floating-point
SNR
trtmcation error
FPGA
