期刊文献+

体硅CMOS FinFET结构与特性研究 被引量:1

Bulk Silicon CMOS FinFET's Structure and Characteristics
下载PDF
导出
摘要 建立在SOI衬底上的FinFET结构被认为是最具全面优势的非常规MOS器件结构.本文通过合理的设计将FinFET结构迁移到普通体硅衬底上,利用平面凹槽器件的特性解决了非绝缘衬底对器件短沟道效应的影响,同时获得了一些标准集成电路工艺上的改进空间.运用标准CMOS工艺实际制作的体硅CMOSFinFET器件获得了较好的性能结果并成功地集成到CMOS反相器和环形振荡器中.结构分析与实验结果证明了体硅CMOSFinFET在未来电路中的应用前景. Original SOl FinFET was considered as the best candidate among various non-classic MOS structures. This paper firstly built a FinFET structure on normal bulk - Si substrate by a reasonable design. The SCE of FinFET fabricated on the non-insulating substrate was suppressed greatly for the existing of a grooved planar device by parallel connection. In addition, this new structure provided more process space than original SOl FinFET. The devices, which were fabricated with a standard CMOS process, showed a good performance and were integrated into a small-scale circuit successfully.The results demonstrated that bulk-Si FinFET was a good solution for future VLSI.
出处 《电子学报》 EI CAS CSCD 北大核心 2005年第8期1484-1486,共3页 Acta Electronica Sinica
基金 国家自然科学基金(No.60176010) 国家重点基础研究973项目(No.TG2000036504)
关键词 鱼脊形场效应晶体管 体硅 凹槽器件 新结构 CMOS finFET bulk-si grooved device novel structure CMOS
  • 相关文献

参考文献7

  • 1Semiconductor Industry Association. International Technology Roadmap for Semiconductors,2001 Editions[S].
  • 2H S PHILIP WONG, D J Frank, et al. Nanoscale CMOS[J]. Proc of the IEEE, 1999,87(4) :537 - 584.
  • 3J H LEE, G Taraserli, Andy Wei, et al. Super Self-Aligned Double Gate (SSDG) MOSFETs Utilize Oxidation Rate Difference and Selective Epitaxy [A]. IEEE Tech. Dig. IEDM[ C]. Washington,2001.71 - 74.
  • 4T SU,J P Denton, et al. New planar serf-aligned double-gate fully dephted P-MOSFET's using epitaxial lateral overgrowth (ELO) and selectively grown source/drain (S/D)[A]. IEEE Int SOI Conf[C].Toyto,2000.110 - 111.
  • 5X HUANG,W C Lee,C Kuo, et al. Sub-50nm P-channel FinFET[J].IEEE Trans E D,2001,48(6):880-886.
  • 6任红霞,郝跃.槽栅MOS器件的研究与进展[J].微电子学,2000,30(4):258-262. 被引量:1
  • 7M Mehrotra,J C Hu,et al.A 1.2V,sub-90nm gate length CMOS technology[ A] .IEEE Tech. Dig. IEDM[ C]. Washington, 1999.419-422.

二级参考文献5

  • 1Lee W H,IEEE Elec Dev Lett,1993年,14卷,12期,578页
  • 2孙自敏,半体技术,1998年,23卷,5期,18页
  • 3许冬岗,深亚微米槽栅器件特性及抗热载流子效应研究[D],1998年
  • 4Yu B,IEEE Trans Electron Dev,1997年,44卷,4期,627页
  • 5Chan M,IEEE Elec Dev Lett,1994年,15卷,1期,22页

同被引文献11

  • 1黄伟,张利春,高玉芝,金海岩.掺Mo对NiSi薄膜热稳定性的改善[J].物理学报,2005,54(5):2252-2255. 被引量:4
  • 2黄伟,张利春,高玉芝,金海岩,卢建政,张慧.Ni(Pt)Si硅化物温度稳定性的研究[J].固体电子学研究与进展,2005,25(3):422-426. 被引量:7
  • 3蔡一茂,黄如,单晓楠,周发龙,王阳元.锗预非晶化注入对镍硅(NiSi)金属栅功函数的影响研究[J].电子学报,2006,34(8):1534-1536. 被引量:1
  • 4Zhang S H,et al.Metal silicides in CMOS technology:past,present,and future trend[J].Critical Reviews in Solid State and Material Science,2003,28(1):1-129.
  • 5Lee P S,Pey K L,Mangelinck D.New salicidation technology with Ni(Pt) alloy for MOSFETs[J].IEEE Electron Device Lett,2001,22(12):568-570.
  • 6Liu J F,Chen H B,Feng J Y.Enhanced thermal stability of NiSi films on Si(111) substrates by a thin Pt interlayer[J].Journal of Crystal Growth,2000,220:488-493.
  • 7Lee P S,Pey K L,Mangelinck D.Improved NiSi salicide process using presilicide N+2 implant for MOSFETs[J].IEEE Electron Device Lett,2001,21(12):566-568.
  • 8Huang W,Zhang L C,Gao Y Z.The improvement of thermal stability of nickel silicide by adding a thin Zr interlayer[J].Microelectronic Engineering,2006,83(2):345-350.
  • 9Yue X W,Zhang L C,Gao Y Z.A Hafnium interlayer method to improve the thermal of NiSi film[J].Microelectronic Engineering,2008,85(2):1723-1727.
  • 10汪金辉,宫娜,耿淑琴,侯立刚,吴武臣,董利民.45nm低功耗、高性能Zipper CMOS多米诺全加器设计[J].电子学报,2009,37(2):266-271. 被引量:9

引证文献1

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部