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基于锁相环的10.709 Gbit/s时钟数据再生模块 被引量：1

10.709 Gbit/s CDR Based on Phase Locked Loop
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摘要 作者采用D-FF触发器、鉴相器和VCO构成的锁相环,研制出了码率为10.709 Gbit/s的时钟数据再生模块.该模块的中心工作码率可在9.5～11 Gbit/s之间设定,锁定带宽Δf≈110MHz,输入信号幅度VINp-p80～1600mV,输出信号幅度VD-p-p≈900mV,输出信号抖动均方根值JD-RMS≈1.5～1.6ps、抖动峰峰值JD-p-p≈7～8ps. Using a D-FF, phase comparator and VCO, the authors produced a 10.709 Gbit/s CDR based on PLL. The operating frequency of the CDR can be set within 9.5 - 11GHz,the lock bandwidth △f is about 110 MHz, the amplitude of input signal VINP-P is 80 - 1600mV,the amplitude of output data VD-P-P is about 900mV,the jitter RMS of output data JD-p-p is 1.5 - 1.6ps and the peak-to-peak jitter of output data JD-P-P is 7 - 8ps.
作者 王勇 姚宏颖 王子宇
机构地区 北京大学电子学系区域光纤通信网与新型光通信系统国家重点实验室
出处 《电子学报》 EI CAS CSCD 北大核心 2005年第8期1509-1511,共3页 Acta Electronica Sinica
基金 国家863计划(No.2003AA103610)
关键词 时钟数据再生 10.709 Gbit/s光接收机 锁相环 CDR 10.709 Gbit/s optical receivers phase locked loop
分类号 TN305 [电子电信—物理电子学]
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参考文献9

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同被引文献16

  • 1Zhang Xiaowei,Hu Qingsheng.A 6.25Gbps CMOS 10B/8B decoder with pipelined architecture[J].Journal of semiconductors,2011,32(4):045009-1-4.
  • 2Jayesh Patil,Lili He,Morris Jones.Clock and data recovery for a 6 Gbps SerDes receiver[A].Conference on Computer Science and Information Technology[C].Chengdu:IEEE,2010.217-221.
  • 3Sally Safwat,Ezz El-Din Hussein,Maged Ghoneima,et al.A 12Gbps all digital low power SerDes transceiver for on-chip networking circuits and systems[A].International Symposium on Circuits and Systems[C].Rio de Janeiro:IEEE,2011.1419-1422.
  • 4Mike Harwood,Steffen Nielsen,Andre Szczepanek,et al.A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications[A].2012 IEEE International Solid-State Circuits Conference Digest of Technical Papers[C].San Francisco:IEEE,2012.326-327.
  • 5Jri Lee,Behzad Razavi.A 40-Gb/s clock and data recovery circuit in 0.18μm CMOS technology[J].IEEE Journal of Solid-State Circuits,2003,38(12):2181-2190.
  • 6Young-Ho Kwak,Yongtae Kim,Sewook Hwang,et al.A 20 Gb/s clock and data recovery with a ping-pong delay line for unlimited phase shifting in 65nm CMOS process[J].IEEE Transactions on Circuits and Systems Ⅰ:Regular Papers,2013,60(2):303-313.
  • 7Arash Zargaran-Yazd,Shahriar Mirabbasi.12.5-Gb/s full-rate CDR with wideband quadrature phase shifting in data path[J].IEEE Transactions on Circuits and Systems Ⅱ:Express Briefs,2013,60(6):297-301.
  • 8Ansgar Pottb(a)cker,Ulrich Langmann,Hans-Ulrich Schreiber.A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s[J].IEEE Journal of Solid-State Circuits,1992,27 (12):1747-1751.
  • 9Zhou Mingzhu,Sun Lingling,Wang Guangyi,et al.Designing 3.125GHz bang-bang PLL for clock recovery in 6.25 Gbps backplane communication receiver[A].2010 International Conference on Microwave and Millimeter Wave Technology[C].Chengdu:IEEE,2010.639-942.
  • 10Jafar Savoj,Behzad Razavi.A 10-Gb/s CMOS clock and data recovery circuit with a half-rate Binary phase/frequency detector[J].IEEE Journal of Solid-State Circuits,2003,38 (1):13-21.

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电子学报
2005年 第8期

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