摘要
针对高速串行数据可靠接收问题,设计了一种高速串行接收电路结构。对比以往文献中的电路,它的适应条件更加宽松,同时性能提高了50%。经过软件仿真和硬件实测,它能在高达310Mbit/s的串行数据速率下稳定工作。这在实际高速数据传输系统中具有广泛的应用价值。
A structure for 300Mbit/s serial data recovery was advanced. Compared with the circuits in the references, this scheme can be used with less limits and achieve performance one second higher. It was proved to work well at its peak speed of 310Mbit/s serial data flow through both the software simulation and the hardware testing. This structure will have a very wide usage in high-speed data transition systems.
出处
《通信学报》
EI
CSCD
北大核心
2005年第8期78-83,共6页
Journal on Communications
关键词
数字电路
高速串行数据
可靠接收
FPGA
digital circuits
high-speed serial data transition
data recovery
FPGA
