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W-CDMA系统中维特比译码器的FPGA实现 被引量:1

The implementation of viterbi decoder in W-CDMA system using FPGA
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摘要 W-CDMA系统中采用约束长度为9的卷积编码作为信道编码方案之一,维特比译码器是被一种人们广泛采用的卷积编码的解码器;本文通过分析卷积编码及维特比译码的过程,介绍一种适合WCDMA系统中软判决维特比译码器实现的硬件结构。 W - CDMA System adopts Convolutional Code - Constranit length of 9 as one of the Channel - Coding Schemes. In practice, Viterbi Decoder is a popular decoder for Convolutional code. This article analyzes the Convolutional coding and Viterbi decoding and presents a hardware structure of the soft - decision Viterbi Decoder suited for W - CDMA System.
出处 《西安邮电学院学报》 2005年第3期27-30,共4页 Journal of Xi'an Institute of Posts and Telecommunications
关键词 W-CDMA 信道编码 维特比译码器 FPGA ASIC W - CDMA Channel - Coding Viterbi Decoder FPGA ASIC
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参考文献5

  • 1Texas Instruments. Viterbi Decoding Techniques in the TMS320C54x Family,2000.
  • 2Lou H- L. Implementing the Viterbi algorithm[J ]. IEEE Signal Processing Magazine, 1995.42 - 52.
  • 3Lapidoth. On the probability of symbol error in Viterbi decoders[ J ]. IEEE Trans Communicaitons, 1997: 45 (1):152 - 155.
  • 4Jany- Hyun Park and Yea- Chul Rho. Performance Test of Viterbi Decoder for Wideband CDMA System.Proceedings of the ASP - DAC ' 97 Asia and South Pacific,1997:19 - 23.
  • 5M. Zalfany Urfianto(zanlfnay@opencores. org). VDK9 R1/2 Design document-Version 1.00,2001.

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