摘要
介绍一种在CLA基础上改进的快速加法器算法设计。文中详细阐述了该算法的推导,以及部分硬件实现电路图,并对输入为两个106比特操作数的加法器进行了性能仿真,从仿真结果可以看出,新的加法器算法使先行进位加法器的速度得到很大的提高。
This thesis introduces an improved fast adder algorithm based on CLA, and expounds its developing process in detail, as well as part of its circuit diagram. The performance of two 106 bits operands adder is simulated, and from the simulation results we can conclude the adder has many improvement in speed.
出处
《西安邮电学院学报》
2005年第1期6-9,共4页
Journal of Xi'an Institute of Posts and Telecommunications
基金
陕西省自然科学基金资助项目(项目编号:20001X13)
