循环纠错码的VHDL语言实现

VHDL Realization of Cyclical Error-correct Coder and Decoder

探讨了循环纠错码编译码器的VHDL语言的FPGA实现.用语言描述实现的循环纠错编和译码器比用硬件电路实现后再下载到可编程电路的方法有更强的适应性.对于(n,k)循环纠错码,只要确定了n和k的值就可以按此方法实现设计.

The VHDL based FPGA design for implementing cyclical error-correct coder and decoder is inquired into. The realization is more adaptive than the FPGA ones based on circuit. For any given （n, k） cyclical error-correct code, what has to do is only to change the scale of the design.