DVB传输流PCR抖动检测的FPGA实现

The Implement of FPGA Based on PCR Jitter Measurement of DVB TS

主要研究利用FPGA实现DVB码流检测的方法,首先介绍PCR抖动的基本原理及其形成原因,接着阐述系统工作流程以及结构。该设计模块由VHDL语言完成,并通过了系统验证。

This paper mainly focus on the measurement of PCR jitter in DVB TS using FPGA. Firstly introduce principles and cause of PCR jitter. Then describe the flow and structure of system. The system modules is described in VHDL. The result of synthesis and implement demonstrates the system functionality.