基于VHDL语言的组合乘法器设计与仿真

Design and Simulation of Combinational Multiplier Based on VHDL Language

基于VHDL的数字系统设计具有设计技术齐全、方法灵活、支持广泛等优点,同时也是EDA技术的重要组成部分。文章用VHDL语言设计了左移法和进位节省法实现的两种组合乘法器,通过功能仿真,对两种乘法器的性能进行了比较,从而得知后者的传输延迟时间小,即速度较快。通过设计实例,介绍了利用VHDL语言进行数字系统设计的方法。

Digital systems using VHDL has the advantages of comprehensive design technologies, flexible design methods and wide range support,lt＇s also an important component of EDA. The combinational multipliers to use two methods of left shifts and carrysave are designed in VHDL language, by functional simulation, comparing the peculiarity of two multipiers, find the carry-save multiplier＇s delay shorter ,speed faster. Through design examples ,this paper introduces the method of digital systems design based on VHDL.