用于密码芯片抗功耗攻击的功耗平衡加法器

DPA Resistant Power-Balanced Adder for a Cryptographic IC

给出了一种用于密码芯片以提高芯片抗功耗攻击能力的“功耗平衡”加法器,它运行时工作功率与运算数据无关.对新设计与相关原设计芯片的功率样本进行显著性检验,在样本数为283的情况下,前者的最低显著性水平比后者高10个数量级.功耗平衡加法器比现有的采用“n分之一”编码的抗功耗攻击加法器少13个以上的晶体管.

A power-balanced DI carry-lookahead adder, whose power is influenced little by the input data,can be used in a cryptographic IC to counter the power analysis. Power significances of implementations of this circuit and a contrasted DI adder are tested, yeilding a significant probability of the former of about 10^10 times of that of the later. The number of transistors of this adder is to a lesser degree 13 over than the existing logic level solutions.