摘要
设计了一种用于10/100Base-T以太网收发器的频率综合器电路.该电路自适应工作在10和100Mbps两种模式下,并能自由切换.电路采用cascode电流源、差分对称负载延迟单元等优化结构,使时钟输出具有良好特性,且能兼具DLL功能,同时满足发送电路上升下降斜率控制和时钟恢复电路对于多相时钟的需要,避免额外的功耗和面积.在一定测试环境下,晶振的cycle-cycle抖动σ约为25ps,输出时钟分频后的25MHz测试时钟信号的σ仅为22ps.测试结果表明,时钟发生电路具有良好的工艺稳定性和较强的抑制噪声能力,满足发送和接收电路对于时钟性能的要求.芯片采用SMIC0.35μm的标准CMOS工艺,电源电压为3.3V.
A frequency synthesizer applied to a 10/100Base-T ethernet transceiver is described. It can work adaptively in either a 10Mbps or 100Mbps mode and convert freely from one mode to another. Cascode current sources and differential delay cells are adopted to guarantee good performance. The circuit meets the requirements of both transmitter on rising/falling time and receiver on CDR so that additional power and area are saved. Under some testing circumstance, σ of voltage control oscillator jittercycle-cycle is only 22ps with σ of reference clock jittercycle-cycle 25ps. The testing results prove that the frequency synthesizer has good processing stability and rejection to various noises. It works well for both transmitters and receivers. The circuit is designed with SMIC 0.35μm standard CMOS technology and a power supply of 3.3V.
关键词
以太网
频率综合器
时钟抖动
ethernet
frequency synthesizer
clock jitter
