静态时序分析在数字ASIC设计中的应用

The Application of Static Timing Analysis (STA) in Digital ASIC Design

主要介绍了静态时序分析在数字ASIC设计中的应用,描述了静态时序分析的基本原理和流程,并以I2C总线设计为例,分析了对数字ASIC作静态时序分析中可能出现的问题,提出了消除虚假路径的实际方法.通过对全芯片进行静态时序分析,可以确认设计的准确性和可靠性,从而为设计流程中每一部分的工作取得sign-off提供可靠保证.

This paper introduces the application of static timing analysis （STA） in digital ASIC design, describes the basic principles and flows of STA, analyzes the possible problems in the STA analysis for digital ASIC with the design of I^2C bus as an example, and puts forward the practical methods to eliminate the false path. Through the STA for the full chip, the veracity and reliability of the design can be validated, and the sign - off has been obtained for each part of the work in the design flow.