摘要
针对当今电子系统对高速大容量内存的需要,本文阐述了使用DDR控制器IP核来设计实现DDR内存接口的方法。该方法能使设计尽可能简单,让设计者更专注于关键逻辑设计,以便达到更高的性能。该设计经过仿真显示,完全符合要求。
To meet the need of the high-speed and big-capacity memory in electrical system , the design and implement of the DDR memory interface using DDR controller IP core was introduced in this paper. This method made the design simple as possible as it. It also made the designer be absorbed in the critical-logic design. Emulating wave shows that this design is up to the demands completely.
出处
《微计算机信息》
北大核心
2005年第08Z期102-103,41,共3页
Control & Automation
基金
国家863计划(2003AA103510)资助项目