一种基于FPGA实现的FFT结构

An FFT Architecture for FPGA Implementation

本文讨论了一种可在FPGA上实现的FFT结构。该结构采用基于流水线结构和快速并行乘法器的蝶形处理器。乘法器采用改进的Booth算法,简化了部分积符号扩展,使用Wallace树结构和4-2压缩器对部分积归约。以8点复点FFT为实例设计相应的控制电路。使用VHDL语言完成设计,并综合到FPGA中。从综合的结果看该结构可在XC4025E-2上以52MHz的时钟高速运行。在此基础上易于扩展为大点数FFT运算结构。

An FFT Architecture implemented in FPGA is described in this paper. This FFT Architecture is based on a butterfly process which employs pipeline architecture and fast parallel multiplier.This multiplier used modified Booth Algorithm, Wallace tree and 4-2 compressor. A control unite is designed for eight points FFT. The FFT structure is written in VHDL and is synthesized in FPGA. The synthesis results show this FFF structure can run at 52MHZ clock rate in XC4025E-2. This FFT structure is easy to expand more points FFT structure.